Samsung Electronics develops 3D chip packaging technology

7 October 2019 (Last Updated October 7th, 2019 15:03)

South Korean multinational electronics company Samsung Electronics has developed a 12-layer 3D Through Silicon Via (TSV) chip packaging technology.

South Korean multinational electronics company Samsung Electronics has developed a 12-layer 3D Through Silicon Via (TSV) chip packaging technology.

The packaging innovation will involve vertically interconnecting 12 DRAM chips through a three-dimensional configuration of more than 60,000 TSV holes.

The new technology will offer identical capability with the same thickness (720µm) as the current eight-layer high-bandwidth memory-2 (HBM2) products.

The 3D-TSV technology will enable the mass production of high-performance chips.

Samsung Electronics test and system package executive vice-president Hong-Joo Baek said: “Packaging technology that secures all of the intricacies of ultra-performance memory is becoming tremendously important, with the wide variety of new-age applications such as artificial intelligence (AI) and high-power computing (HPC).

“As Moore’s law scaling reaches its limit, the role of 3D-TSV technology is expected to become even more critical. We want to be at the forefront of this state-of-the-art chip packaging technology.”

The 3D packaging technology will allow customers to release high-performance products with increased capacity, using the existing system configuration designs.

The new system has significantly improved, comparing to the existing wire-bonding technology since it reduces data transmission time between chips.

This increases speed and reduces power consumption.

Samsung noted that the 12-layer 3D-TSV technology will offer increased DRAM performance for high-speed and data-intensive applications.

The technology will enable the company to mass-produce 24GB high-bandwidth memory.

The company expects to meet the growing demand for high-capacity HBM solutions.