Through this programme, the US Government will take advantage of Intel ’s US manufacturing capabilities.
The company’s advanced heterogeneous packaging technologies include embedded multi-die interconnect bridge (EMIB), 3D Foveros and Co-EMIB (combining both EMIB and Foveros).
The heterogeneous packaging assembles multiple and separately produces integrated circuit dies (chips) into a single package.
This lowers power, size and weight, while enhancing performance.
“The SHIP programme will enable the Department of Defence to take advantage of Intel ’s advanced semiconductor packaging capabilities, diversifying their supply chain and protecting their intellectual property while also supporting on-going semiconductor R&D in the US and preserving critical capabilities onshore.”
Administered by the National Security Technology Accelerator, the project is executed by the Naval Surface Warfare Centre, Crane Division.
Sponsored by the Office of the Under Secretary of Defense for Research and Engineering, SHIP is funded by the Trusted and Assured Microelectronics programme.
Under the second phase of the programme, multiple packages prototypes will be developed.
The prototypes will see the combining of Intel ’s advanced, commercially available silicon products with special-purpose government chips.
Office of the Under Secretary of Defence for Research and Engineering microelectronics principal director Nicole Petta said: “The roadmap also prioritises and recognises that as process scaling slows, heterogeneous assembly technology is a critical investment for both the DOD and our nation.
“SHIP directly contributes to advancing the objectives outlined in the DOD roadmap and the DOD looks forward to working with Intel , a world leader in this technology.”